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Old 04-05-13, 06:45 PM   #1
ALK
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Default I you help on VHDL program

I have to design State machine from 5-bits UP/DOWN Counter(2 BCD numbers). also i have to use 5-DFF, because their are 5-bits; Design a state machine for a digital system that counts the number of people in a room. People enter
the room from one door with a photocell that changes a signal x fro 1 to 0 when the light is interrupted.
They leave the room from a second door with a similar photocell with a signal y. Both x and y are
synchronized with the clock, but they may stay on or off for more than one clock pulse period. The
data processor subsystem consists of an up-down counter with a display of its content.
# HERE IS MY CODE COULD ANY ONE CAN HELP, THANK YOU.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_UNSIGNED.all;

entity Counter2 is
port (Clock_enable_B : in std_logic;
Clock : in std_logic;
Reset : in std_logic;
x, y : in std_logic;
output : out std_logic_vector (0 downto 4));
end Counter2;

architecture Behavioral of Counter2 is
signal temp : std_logic_vector (0 downto 4);
begin process (Clock, Reset, Clock_enable_B, x, y)

begin
if Reset = '1' then
temp <= "00000";
elsif (Clock'event and Clock = '1') then
if Clock_enable_B='0' then
if x = '0' then
if temp="11001" then
temp<="00000";
if temp="01001" then
temp<="10000";
else
temp <= temp + 1;
if y = '0' then
temp <= temp -1;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
output <= temp;
end Behavioral;

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