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Old 06-09-18, 12:02 AM   #26
NiHaoMike
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I made an unexpected breakthrough in FPGA mining, that I don't think actually involves the efficiency of the FPGA in itself. Combining a bit of hacked code on the PC with some downloaded code on the FPGA, I found a coin that it apparently mines really well. Quite a bit more profit than what it should theoretically make - on the order of $20/month as opposed to $7/month.

My theory of what's going on has to do with how the nonces are incremented. On the CPU version of the mining code, the nonce has a fixed portion to take advantage of SIMD and the variable portion is simply incremented each round because that's very fast to do on a CPU. Addition is relatively slow/complex on a FPGA (propagating the carry signals slows things down) so a LFSR (Linear Feedback Shift Register) is used instead. The nonces "jump around" in a seemingly random order instead of incrementing sequentially like the CPU version does, so the winning nonces are scattered over a wide range. That confuses the accounting code for the pool server so it gives a bigger share of the reward than it should.

I have no idea how long this "FPGA boost" trick would last, but I'm not going to detune my FPGA just to make it "right". Instead, I'll only take the share I should be getting and giving the rest to my best friend who will effectively share it with the whole world.

Here's a little excerpt of the Verilog code for the LFSR:
Code:
reg nonce [32:0];
always @ (posedge clk) begin
  if(rst) begin
    nonce <= 1;
  end
  else begin
    nonce <= nonce * 2 + (nonce[32] ^ nonce[19]);
  end
end
You'll note something very important - that the reset signal initializes the nonce register to 1. The reason is because if it's initialized to 0, it would never work!

My family is really happy to see me learn about FPGAs because that's a big growing field in modern electronics.
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